module cache (	input [4:0] AlCa_address,
				input [63:0] SysFe_data,
				input AlCa_we,
				input clk,
				input Rst_Ca,
				input stop,
				output hit,
				output [15:0] data_out);
reg hit;
always @ (posedge clk)
begin
	hit = 0;
end
endmodule
